Shock sensor circuitry and method for amplifying an input signal including leakage currents

ABSTRACT

A shock sensor circuitry (26) is provided for processing an input signal generated by a shock sensor (28) in response to the shock sensor (28) detecting a force or shock. The shock sensor circuitry (26) includes a leakage tolerant input amplifier (38) for receiving the input signal, and any leakage currents that may also be provided, and amplifying the input signal to generate an amplified input signal. The leakage tolerant input amplifier (38) provides an ac gain of ten and a dc gain of zero. The shock sensor circuitry (26) also includes a filter and amplification circuit and a window comparator. The filter and amplification circuit filters the amplified input signal and amplifies select frequencies of the amplified input signal to generate a summed signal that is provided to the window comparator and compared to a reference value. The window comparator includes an upper comparator (58), a lower comparator (60), and an output circuit (62) to generate a shock sensor circuitry output signal that indicates whether a shock or force was received at a magnitude greater than the reference value.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to the field of electronic circuitryand more particularly to a shock sensor circuitry including a leakagetolerant input amplifier and a method for amplifying an input signalincluding leakage currents.

BACKGROUND OF THE INVENTION

Shock sensor circuitry may be used in electronic devices to detect theapplication of a shock or force to an electronic device. For example,the hard disk drives of portable electronic devices, such as laptop andnotebook computers, may include shock sensor circuitry to detect theapplication of a force such as that caused by dropping or bumping thecomputer. If a great enough force is applied, usually greater than oneG, a hard disk drive may incorrectly write data during a write operationor incorrectly read data during a read operation. This results in dataerrors and sometimes system failure.

The shock sensor circuitry generally senses or detects the force andgenerates an output signal in response. As a result of generating theoutput signal, an action may be taken to prevent or minimize problemscaused by the force. For example, the shock sensor circuitry of a harddisk drive may generate a signal to temporarily suspend a writeoperation or read operation to eliminate or minimize any adverse effectsthat may be caused by the force.

The shock sensor circuitry receives and processes an input signalgenerated by a shock sensor. The shock sensor is generally constructedfrom a piezoelectric material and has a high impedance. The shock sensorgenerates an input signal at a very low voltage that corresponds to theshock or force detected. The input signal must be amplified before it isprocessed by the shock sensor circuitry.

Problems arise when amplifying this low voltage input signal providedfrom the high impedance shock sensor. Specifically, direct currentleakage currents are often present in addition to the input signal.These leakage currents are amplified, along with the input signal, by aninput amplifier or input stage of the shock sensor circuitry resultingin an offset voltage that creates errors within the shock sensorcircuitry. These errors may result in the generation of output signalsindicating that a force was detected when none was present or thegeneration of an output signal indicating that no force was detectedwhen one was present.

The leakage currents may be generated by a variety of sources and arepresent at some level in virtually all semiconductor junctions.Oftentimes, electrostatic discharge circuitry or structures are providedat the pins of an integrated circuit. The electrostatic dischargecircuitry provides enhanced circuitry protection from electrostaticdischarge which can destroy an integrated circuit. Integrated circuitsusing MOSFET technology are particularly susceptible to electrostaticdischarge damage. As a consequence of providing the electrostaticdischarge circuitry, a current path is provided resulting in increasedleakage currents and decreased shock sensor circuitry performance. Forexample, a standard operational amplifier with an electrostaticdischarge circuitry at its pins may draw a direct current leakagecurrent of ten picoamps at room temperature and from one to ten nanoampsat 125° C. Leakage currents increase with an increase in temperature.Reliability suffers greatly if the electrostatic discharge circuitrymust be removed to help reduce the leakage currents.

Other sources of leakage currents include current leakage frompin-to-pin across the plastic package of an integrated circuit and fromthe contamination present on most printed circuit boards. Printedcircuit board contamination may include dust, particles, and any foreignor undesirable material on the printed circuit board that may provide apath for leakage currents. Contamination may result in leakage currentsin the picoamp to nanoamp range, depending on the level ofcontamination. The contamination may only be eliminated or reduced bysubjecting the printed circuit boards to additional cleaning processesthat are both expensive and time consuming and significantly add tooverall costs. Even if the contamination is initially removed, theprinted circuit boards may later become contaminated resulting inincreased leakage currents and decreased shock sensor circuitryperformance.

SUMMARY OF THE INVENTION

From the foregoing it may be appreciated that a need has arisen for ashock sensor circuitry and method for amplifying an input signalincluding leakage currents to eliminate or reduce the problemsassociated with the leakage currents. In accordance with the presentinvention, a shock sensor circuitry and method for amplifying an inputsignal including leakage currents are provided.

According to the present invention, a shock sensor circuitry is providedfor processing an input signal generated by a shock sensor in responseto the shock sensor detecting a force or shock. The shock sensorcircuitry includes a leakage tolerant input amplifier having a directcurrent gain of around zero for receiving the input signal, and anyleakage currents that may also be provided, and generating an amplifiedinput signal. The shock sensor circuitry further includes a filtercircuit for filtering the amplified input signal and amplifying selectfrequencies of the amplified input signal to generate a filtered signalthat is provided to a comparator. The comparator compares the filteredsignal to a reference value to determine if a shock or force with amagnitude greater than the reference value has been received. Thecomparator generates a shock sensor circuitry output signal in anenabled state if the filtered signal has a magnitude greater than thereference value.

According to another aspect of the present invention, a leakage tolerantinput amplifier is provided for receiving an input signal and an offsetsignal, generated from a direct current leakage current, and forgenerating an amplified input signal in response that is provided at ornear zero when the offset signal is provided at a constant level. Theleakage tolerant input amplifier includes an amplifier, an outputdevice, a first current mirror circuitry, and a second current mirrorcircuitry. The amplifier receives and amplifies the input signalreceived across its input terminals and the offset signal received at anon-inverting input terminal and generates an amplified signal at anoutput terminal. The output device receives the amplified signal andregulates a control current in response. The first current mirrorcircuitry receives a bias current and mirrors the bias current to theoutput device and to an output node. The second current mirror circuitryreceives the control current from the output device and mirrors thecontrol current to the output node. The output node provides theamplified input signal at a value corresponding to the differencebetween the bias current and the control current, and the output deviceregulates the control current to a level that is about equal to the biascurrent when the offset signal is provided at a constant value.

The present invention provides various technical advantages. A technicaladvantage of the present invention includes the ability to receive andtolerate leakage currents without suffering the problems caused by theresulting offset voltages generated in response to receiving the leakagecurrents. These problems include decreased shock sensor circuitryaccuracy, errors, and system performance, such as decreased overall harddisk drive system performance. Another technical advantage of thepresent invention includes reduced overall shock sensor circuitrycomplexity due to the elimination or reduction of offset voltagesgenerated in response to the leakage currents. These offset voltages areeliminated or reduced by the leakage tolerant input amplifier. Stillanother technical advantage includes the ability to use electrostaticdischarge circuitry to increase overall shock sensor circuitryreliability and system reliability even though the electrostaticdischarge circuitry may increase leakage currents. Yet another technicaladvantage of the present invention includes the ability to tolerateleakage currents generated due to contaminated or unclean printedcircuit boards. Still another technical advantage includes decreasedoverall costs due to the elimination of the added steps and processesneeded to clean contaminated printed circuit boards so as to eliminateor reduce the presence of leakage currents. Other technical advantagesare readily apparent to one skilled in the art from the followingfigures, description, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following briefdescription, taken in connection with the accompanying drawings anddetailed description, wherein like reference numerals represent likeparts, in which:

FIG. 1 is a block diagram illustrating a hard disk drive;

FIG. 2 is a circuit diagram illustrating a shock sensor circuitry of thehard disk drive; and

FIG. 3 is a circuit diagram illustrating a leakage tolerant inputamplifier of the shock sensor circuitry.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a block diagram illustrating a hard disk drive 10. Hard diskdrive 10 includes a plurality of disk platters 12 for magneticallystoring information, a spindle 14 for rotating plurality of diskplatters 12, a set of read/write heads 16 for reading and writinginformation from and to plurality of disk platters 12, an actuator motorknown as a voice coil motor (VCM) (not shown in FIG. 1) for positioningread/write heads 16 during read and write operations, and a spindlemotor (also not shown in FIG. 1) for rotating spindle 14 to impartrotational motion to plurality of disk platters 12. Read/write heads 16fly above the surface of each side of the platters of plurality of diskplatters 12 and are mounted on actuator arms which are moved in unisonby the VCM. Read/write heads 16 read data from a platter or disk ofplurality of disk platters 12 by sensing the magnetic flux changes onthe magnetic surface of the platters as it passes beneath a read/writehead of read/write heads 16.

Hard disk drive 10 further includes a preamplifier 18, a read channel20, a hard disk drive (HDD) microcontroller 22, a servo integratedcircuit (IC) 24, and a shock sensor 28. Servo IC 24 may be implementedas either a servo controller or a servo driver. Preamplifier 18 is usedto amplify analog data signals being provided between read channel 20and read/write heads 16 during read and write operations. Read channel20 processes the analog data signals and converts them from analog datasignals to corresponding digital data signals during read operations.Read channel 20 converts digital data signals received from HDDmicrocontroller 22 to corresponding data signals during writeoperations. Read channel 20 exchanges the digital data signals with HDDmicrocontroller 22 and the analog data signals with preamplifier 18.Read channel 20 may also exchange control signals and servo informationwith servo IC 24. Servo IC 24 controls the speed of the spindle motorand the positioning of read/write heads 16 by controlling the VCM duringread and write operations.

HDD microcontroller 22 provides overall control of hard disk drive 10and controls the initiation of read and write operations. HDDmicrocontroller 22 allows data to be exchanged between hard disk drive10 and a system bus, such as the system bus of a personal computer andmay provide some digital signal processing capability. A random accessmemory, both static and dynamic, may also be provided for storing dataand routines. HDD microcontroller 22 also interfaces with servo IC 24 toexchange control information. For example, a servo sensor circuitry 26of servo IC 24 may provide a shock sensor circuitry output signal to HDDmicrocontroller 22 that indicates whether a shock or force above areference threshold has been detected. The combined circuitry of shocksensor circuitry 26 and shock sensor 28 are used to generate the shocksensor circuitry output signal. If such a shock is detected, HDDmicrocontroller 22 may interrupt or delay a read or write operation toprevent a data error or system failure. HDD microcontroller 22 makes thedecision whether to stop the read or write operation. For example, ifthe shock sensor circuitry output signal is provided in an enabled stateover a given period of time, HDD microcontroller 22 may disable a writeor read operation until the effect of the shock is reduced.

Shock sensor 28 may be implemented as a piezoelectric shock sensor witha high impedance. Shock sensor 28 generates an alternating current (ac)signal corresponding to the magnitude and direction of a detected shockor force. Leakage currents may also be provided to shock sensorcircuitry 26 at the interface with shock sensor 28. These leakagecurrents often result in the generation of an offset voltage. Shocksensor circuitry 26 includes leakage tolerant input amplifier 38 (notshown in FIG. 1) that prevents the offset voltage from being amplified.

FIG. 2 is a circuit diagram illustrating shock sensor circuitry 26 andshock sensor 28 of HDD 10. Shock sensor circuitry 26 receives an inputsignal from shock sensor 28, including any leakage currents that may beprovided, and generates a shock sensor circuitry output signal that isprovided to HDD microcontroller 22 for further processing and control ofHDD 10. Shock sensor circuitry 26 may be implemented as an integratedcircuit that is included as part of servo IC 24 and includes anelectrostatic discharge circuitry (ESD) 37 and ESD 39 at its pins. ESD37 and ESD 39 are designed to provide added protection from anelectrostatic discharge. Shock sensor 28 will generally be implementedas a high impedance piezoelectric shock sensor that generates a lowvoltage signal having a spectrum of frequencies in response to thedetection of an applied shock or force. The low voltage signal serves asthe input signal to shock sensor circuitry 26 and will generally beprovided as an alternating current (ac) signal having a magnitude andpolarity related to the magnitude and direction or angle, respectively,of the detected shock. The shock sensor circuitry output signalindicates whether a shock or force has been detected having a magnitudegreater than or equal to a predefined level.

A voltage reference 30 couples to both capacitor 32 and to a firstterminal of shock sensor 28. Voltage reference 30 provides a biasvoltage to shock sensor circuitry 26 and shock sensor 28. Capacitor 32may be a 0.82 microfarad capacitor and is provided at the invertinginput terminal of shock sensor circuitry 26 to block dc signals. Asecond terminal of shock sensor 28 couples to a non-inverting inputterminal of shock sensor circuitry 26. A bias resistor 34 couplesbetween the first and second terminal of shock sensor 28 to establish abias voltage to the non-inverting input of leakage tolerant inputamplifier 38. Bias resistor 34 may be provided as a forty-seven megaohmresistor. Capacitor 32 is provided at the inverting input terminal ofshock sensor circuitry 26 to block any dc signal, such as a dc leakagecurrent. As a result, the inverting input terminal of shock sensorcircuitry 26 will only sense the ac portion of the input signalgenerated by shock sensor 28 while the non-inverting input terminal willsense the ac portion of the input signal and any dc leakage currentsthat may be provided through bias resistor 34.

Shock sensor circuitry 26 includes a leakage tolerant input amplifier38, a two pole low pass filter 40, a high pass filter 42, a boostamplifier 44, a summing amplifier 54, an upper comparator 58, and alower comparator 60. A resistor 36 couples between the inverting inputterminal of shock sensor circuitry 26 and an inverting input terminal ofleakage tolerant input amplifier 38. Resistor 36 may be provided as atwenty kiloohm. The non-inverting input terminal of shock sensorcircuitry 26 couples directly to a non-inverting input terminal ofleakage tolerant input amplifier 38. Leakage tolerant input amplifier 38receives the input signal from shock sensor 28 at its terminals, alongwith any leakage currents at the non-inverting input terminal, andamplifies the ac portion of the input signal to generate an amplifiedinput signal having a spectrum of frequencies. Leakage tolerant inputamplifier 38 provides an ac gain of ten and a dc gain of around zero.The amplified input signal is then filtered, amplified, and summed byshock sensor circuitry 26 to generate a summed signal. The summed signalis then compared, using a window comparator, to a range of valuesdefined by an upper and lower reference value to determine if the summedsignal is inside or outside of the range.

Two pole low pass filter 40 receives and filters the amplified inputsignal provided by leakage tolerant input amplifier 38 to generate afiltered signal. Two pole low pass filter 40 removes high frequencynoise and may be a continuous-time RC filter implemented using MOSFETcircuitry that provides a 2 khz corner frequency with a -40decibel/decade rolloff. Capacitor 32 and resistor 36 act as a high passfilter and provide the amplified input signal with a corner frequency.The corner frequency may be provided at around 10 hz with a +20decibel/decade slope. Thus, at the output of the two pole low passfilter 40 a filtered signal is generated having corner frequencies at 10hz and 2 khz with a +20 decibel/decade slope at 10 hz and a -40decibel/decade rolloff at 2 khz.

A high pass filter 42 and a summing amplifier 54 receive and process thefiltered signal from two pole low pass filter 40. High pass filter 42filters the filtered signal and isolates a high frequency portion of thefiltered signal which is then provided to boost amplifier 44 foramplification. High pass filter 42 may be implemented as a buffered,continuous-time RC filter implemented using MOSFET circuitry thatprovides a 1 khz corner frequency with a +20 decibel/decade slope. Thehigh pass filtered signal is then provided to boost amplifier 44 foramplification.

Boost amplifier 44 receives the high pass filtered signal and amplifiesthe signal to generate an amplified high pass filtered signal. Boostamplifier 44 provides a gain of around twenty-five and may be configuredusing as an operational amplifier with feedback. The high pass filteredsignal is provided to a non-inverting input terminal of boost amplifier44 while feedback is provided to an inverting terminal through afeedback resistor 46. A resistor 48 couples between the invertingterminal and voltage reference 30.

Summing amplifier 54 receives the amplified high pass filtered signal atone input and the filtered signal at a second input. The amplified highpass filtered signal is received through a first summing resistor 50coupled to a inverting input terminal of summing amplifier 54, and thefiltered signal is received through a second summing resistor 52 alsocoupled to the inverting input terminal of summing amplifier 54. Summingamplifier 54 includes a feedback resistor 56 coupled between its outputand inverting input terminal, and voltage reference 30 coupled to anon-inverting input terminal. Summing amplifier 54 receives these twosignals and adds them together to generate a summed signal at itsoutput. Summing amplifier 54 may be provided as a variable gainamplifier with a programmable gain. This may be accomplished byproviding a digital signal to a serial port to select a desiredresistance value of feedback resistor 56 to effect a desired gain ofsumming amplifier 54. Selection may be achieved by decode logic whichselects various transmission gates that control the amount of resistanceof feedback resistor 56.

The filtering and amplification of the amplified input signal providedby leakage tolerant input amplifier 38 is needed to extract and amplifyinformation while ignoring input signal information that may provideerroneous information. For example, information provided at or near thefrequency of the spindle motor or the motion of the voice coil motorwill generally be filtered because of the increased risk of detectingthe spindle motor or voice coil motor vibrations.

The summed signal is provided by summing amplifier 54 to an uppercomparator 58 and a lower comparator 60 to determine if the summedsignal is within or out of a range defined by an upper value and a lowervalue. Upper comparator 58 and lower comparator 60 are each comparatorsthat generate a digital output signal in an enabled state when the valueof the signal provided at their positive input terminal is greater thanthe value of the signal provided at their negative input terminal. Theupper value may be equivalent to the sum of voltage reference 30 and 0.5volts while the lower value may be equivalent to the sum of voltagereference 30 minus 0.5 volts. The upper value couples to the negativeterminal of upper comparator 58 and the lower value couples to thepositive terminal of lower comparator 60. The summed signal is providedto the positive terminal of upper comparator 58 and to the negativeterminal of lower comparator 60.

Upper comparator 58 generates an upper shock sensor circuitry outputsignal in an enabled state when the summed signal is greater than theupper value, and the lower comparator 60 generates a lower shock sensorcircuitry output signal in an enabled state when the summed signal isless than the lower value. An output circuit 62 receives the upper shocksensor circuitry output signal and the lower shock sensor circuitryoutput signal and generates a shock sensor circuitry output signal inresponse. Output circuit 62 may be implemented as an OR gate thatgenerates the shock sensor circuitry output signal in an enabled statewhenever either the upper shock sensor circuitry output signal or thelower shock sensor circuitry output signal are provided in an enabledstate.

During steady state operation before a shock is detected and acorresponding input signal is generated by shock sensor 28, the inputsignals provided to shock sensor 28, and hence leakage tolerant inputamplifier 38, are equivalent and the corresponding amplified inputsignal generated by leakage tolerant input amplifier 38 is zero. If aleakage current is present during this time, the leakage current will beprovided through bias resistor 34 to the non-inverting input terminal ofshock sensor circuitry 26. Leakage tolerant input amplifier 38 willignore the leakage current and any offset voltage caused by the leakagecurrent when generating the corresponding amplified input signal. As aresult, the shock sensor circuitry output signal is generated in anunenabled state.

Once a shock is detected, shock sensor 28 generates an ac input signalrelated to the magnitude and direction of the detected shock. The acinput signal is received at the terminals of leakage tolerant inputamplifier 38, along with any leakage current provided to thenon-inverting input terminal of leakage tolerant input amplifier 38, anda corresponding amplified input signal is generated by applying an acgain of ten and a dc gain of zero. The amplified input signal is thenfiltered, amplified, and summed by the combination of two pole low passfilter 40, high pass filter 42, boost amplifier 44, and summingamplifier 54 as described above. The summed signal is then provided toupper comparator 58 and lower comparator 60 so that output circuit 62may generate the shock sensor circuitry output signal in an enabledstate when the summed signal is generated outside of the upper value andlower value. HDD microcontroller 22 may receive the shock sensorcircuitry output signal and take any appropriate action such assuspending a read or write operation to minimize or eliminate anypotential data errors.

Although FIG. 2 illustrates a single shock sensor and associated shocksensor circuitry, multiple shock sensors and associated shock sensorcircuitries may be provided and arranged to detect forces from differentdirections. Each shock sensor may be positioned to detect forces fromdifferent directions. For example, three shock sensors and accompanyingshock sensor circuitries may be provided and arranged to detect forcesapplied in three dimensions such as an x, y, and z direction.

FIG. 3 is a circuit diagram illustrating a leakage tolerant inputamplifier 38 of shock sensor circuitry 26. Leakage tolerant inputamplifier 38 receives an ac input signal generated by shock sensor 28across a non-inverting input terminal and an inverting input terminal asillustrated in FIG. 2 and as discussed above. Leakage tolerant inputamplifier 38 also receives any leakage currents that may be providedfrom any of a variety of sources at its non-inverting input terminal asprovided through bias resistor 34. Leakage tolerant input amplifier 38receives the input signal from shock sensor 28 and generates anamplified input signal in response. The amplified input signal isprovided without any offset voltage that may have been generated due tothe input leakage currents.

ESD 37 and ESD 39 are provided at the input pins of leakage tolerantinput amplifier 38, assuming that leakage tolerant input amplifier 38 isimplemented as an integrated circuit, and are designed to provide addedprotection from an electrostatic discharge. ESD 39 may provide a pathfor dc leakage currents to be provided such that a dc offset voltage isgenerated across bias resistor 34. Capacitor 32 should eliminate orreduce any leakage currents provided to the inverting terminal ofleakage tolerant input amplifier 38.

Leakage tolerant input amplifier 38 includes a standard operationalamplifier (op amp) 66 and a variety of field-effect transistor (FET)devices. The FET devices are used to regulate and mirror variouscurrents such as a bias current I_(BIAS). I_(BIAS) is provided fromcircuitry external to leakage tolerant input amplifier 38 and isprovided as a dc current at, for example, ten microamps.

Many of the FET devices are arranged as transistor pairs with the sameor similar channel dimensions for accurate current mirroring. Forexample, the drain of a FET 72 is coupled to the source of a FET 70 toprovide a cascoded transistor pair so that the I_(BIAS) current providedthrough FET 72 and FET 70 may be mirrored to the transistor pairs thatinclude a FET 74 and a FET 76, and a FET 78 and a FET 80. The transistorpairs of FET 74 and FET 76, and FET 78 and FET 80 are also configured ina cascode configuration so that I_(BIAS) may be more accurately mirroredthrough these transistor pairs. FET 72, FET 74, and FET 78 all includethe same or similar channel dimensions while FET 70, FET 76, and FET 80all include the same or similar channel dimensions.

The combination of FET 70, FET 72, FET 74, FET 76, FET 78, and FET 80may be referred to as a first current mirror circuitry for receiving thecurrent I_(BIAS) and mirroring this current to an output FET 68 and aFET 84. In the embodiment of the first current mirror circuitry shown inFIG. 2, all of the FET devices are implemented as p-channel FETs. Thegates of FET 72, FET 74, and FET 78 are coupled together while the gateand drain of FET 72 are coupled to ensure that the I_(BIAS) currentbeing provided through FET 72 is mirrored through FET 74 and FET 78. Asupply voltage V_(CC) is provided at the source of FET's 72, 74, and 78.Thus, the first current mirror circuitry mirrors the current I_(BIAS)through an output FET 68 and master FET 82 while also mirroring thecurrent I_(BIAS) through FET 84. As a result, the voltage at output node86 is equivalent to the voltage between the drain of FET 80 and thesource of output FET 68 when I_(BIAS) is being provided in the mannerjust described.

The gate of output FET 68 couples to the output terminal of standard opamp 66 and the source of output FET 68 couples to the inverting inputterminal of standard op amp 66. This connection enables output FET 68,as controlled by the output of standard op amp 66, to control orregulate the amount of current flowing through output FET 68. When a dcoffset voltage is provided at the non-inverting input of standard op amp66 due to the presence of a dc leakage current provided through biasresistor 34, the offset voltage is amplified and reflected as anamplified signal at the gate of output FET 68. In response, the sourceof output FET 68 is changed an amount so that the voltage V_(GS) isestablished at a level that allows I_(BIAS) to continue to flow throughoutput FET 68. The feedback connection from the source of output FET 68and the inverting input of standard op amp 66 acts similar to an opencircuit during this state. This results in I_(BIAS) flowing throughoutput FET 68.

When shock sensor 28 provides an ac input signal across the inputterminals of standard op amp 66, the amplified output of standard op amp66 changes with the input signal and the current being provided throughoutput FET 68 changes accordingly to provide a control current throughoutput FET 68. This occurs due to the changing voltage V_(GS) of outputFET 68. The current that is equal to difference between the controlcurrent and I_(BIAS) is provided through the feedback connection betweenthe source of output FET 68 to the inverting input of standard op amp66. Any dc offset voltage provided at the non-inverting input ofstandard op amp 66 will also be provided to the non-inverting input andthus will not be reflected at the output terminal of standard op amp 66.

A second current mirror circuitry is implemented as a transistor pair ofa FET 82 and a FET 84. FET 82 serves as the master and mirrors thecontrol current being provided from output FET 68 to FET 84. As such,output node 86 receives the current I_(BIAS) from FET 76 and the controlcurrent from FET 84 and a difference current is provided through aresistor 88 to generate the amplified input voltage.

Thus, when only a dc offset voltage is provided at the non-invertinginput terminal, the control current is equal to I_(BIAS) and thedifference current is equal to zero. This results in little or nocurrent flowing through resistor 88, and hence, the amplified inputsignal is equal to voltage reference 30. When an ac input signal isprovided from shock sensor 28 at the input terminals of standard op amp66, the control current is not equal to I_(BIAS) resulting in adifference current being provided across resistor 88. This voltage andvoltage reference 30 serve as the amplified input signal. The amplifiedinput signal serves as the output of leakage tolerant input amplifier 38and is provided to two pole low pass filter 40.

Leakage tolerant input amplifier 38 can receive a dc leakage current upto, for example from one to 10 nanoamps at a pin, without generating anoffset voltage at the output of leakage tolerant input amplifier 38.Thus, leakage tolerant input amplifier 38 eliminates the amplificationof a dc offset voltage which prevents the problems associated with a dcoffset voltage generated by the presence of dc leakage currents.

Thus, it is apparent that there has been provided, in accordance withthe present invention, a shock sensor circuitry and method foramplifying an input signal including leakage currents that satisfy theadvantages set forth above. Although the preferred embodiment has beendescribed in detail, it should be understood that various changes,substitutions, and alterations can be made herein without departing fromthe scope of the present invention. For example, although the presentinvention has been illustrated and described as being implemented usingFET or field effect transistor technology, it should be understood thatthe present invention is not so limited. The present invention may beimplemented by one of ordinary skill in the art using a variety of othertechnologies such as bipolar junction transistor technology. Thecircuits described and illustrated in the preferred embodiment asdiscrete or separate circuits may be combined into one circuit or splitinto separate circuits without departing from the scope of the presentinvention. Furthermore, the direct connections illustrated herein couldbe altered by one skilled in the art such that two devices are merelycoupled to one another through an intermediate device or devices withoutbeing directly connected while still achieving the desired resultsdemonstrated by the present invention. Other examples of changes,substitutions, and alterations are readily ascertainable by one skilledin the art and could be made without departing from the spirit and scopeof the present invention as defined by the following claims.

We claim:
 1. A leakage tolerant input amplifier for receiving a firstinput signal and an offset signal, the offset signal generated from adirect current leakage current, and for generating an amplified inputsignal in response to receiving the first input signal, the leakagetolerant input amplifier comprising:an amplifier having a non-invertinginput terminal, an inverting input terminal, and an output terminal, theamplifier operable to receive and amplify the first input signalreceived across its input terminals and the offset signal received atthe non-inverting input terminal to generate an amplified signal at theoutput terminal; an output device operable to receive the amplifiedsignal from the output terminal and to regulate a control current inresponse; a first current mirror circuitry operable to receive a biascurrent and to mirror the bias current to the output device and to anoutput node; and a second current mirror circuitry operable to receivethe control current from the output device and to mirror the controlcurrent to the output node, and wherein the output node provides theamplified input signal at a value corresponding to the differencebetween the bias current and the control current, and the output deviceis operable to regulate the control current to a level that is aboutequal to the bias current when the offset signal is provided at aconstant value.
 2. The leakage tolerant input amplifier of claim 1,wherein the amplifier is an operational amplifier and the invertinginput terminal is coupled to the output device.
 3. The leakage tolerantinput amplifier of claim 2, wherein the output device is a field-effecttransistor having a gate coupled to the output terminal, a sourcecoupled to the inverting input terminal and the first current mirrorcircuitry, and a drain coupled to the second current mirror circuitry.4. The leakage tolerant input amplifier of claim 2, wherein the outputdevice is a field-effect transistor having a gate controlled by theamplified signal, a source operable to receive the bias current mirroredfrom the first current mirror circuitry and to provide feedback to theinverting input terminal, and a drain operable to provide the controlcurrent to the second current mirror circuitry.
 5. The leakage tolerantinput amplifier of claim 1, further comprising:an output resistorcoupled between the output node and a voltage reference, the outputresistor operable to receive an output current from the output node thatis the difference between the bias current and the control current andto generate the amplified input signal in response.
 6. The leakagetolerant input amplifier of claim 5, wherein the voltage reference isground.
 7. The leakage tolerant input amplifier of claim 1, has an acgain of ten and a dc gain of around zero.
 8. The leakage tolerant inputamplifier of claim 1, wherein the bias current is a direct current biascurrent.
 9. The leakage tolerant input amplifier of claim 1, wherein theleakage tolerant input amplifier is provided in an integrated circuitpackage and further comprises:an electrostatic discharge circuitrycoupled to an input pin of the integrated circuit package.
 10. Theleakage tolerant input amplifier of claim 1, wherein the input signal isgenerated by a shock sensor in response to the shock sensor detecting aforce.
 11. The leakage tolerant input amplifier of claim 10, wherein theshock sensor is a piezoelectric sensor operable to generate the inputsignal at a voltage level corresponding to the magnitude of the detectedforce.
 12. The leakage tolerant input amplifier of claim 11, wherein theinput signal is generated between a first terminal and a second terminalof the shock sensor, and the input signal is provided to the amplifieracross the inverting input terminal and the non-inverting inputterminal.
 13. The leakage tolerant input amplifier of claim 12, whereina bias resistor is provided across the first terminal and the secondterminal of the shock sensor, and a capacitor and a resistor areprovided between the first terminal of the shock sensor and theinverting terminal of the amplifier.
 14. The leakage tolerant inputamplifier of claim 1, wherein the input signal is provided as a timevarying signal.
 15. A shock sensor circuitry for processing an inputsignal generated by a shock sensor in response to the shock sensordetecting a force, the shock sensor circuitry comprising:a leakagetolerant input amplifier having a direct current gain of around zero andoperable to receive the input signal including a leakage current and togenerate an amplified input signal in response; a filter circuitoperable to receive the amplified input signal and to filter theamplified input signal to generate a filtered signal; and a comparatoroperable to compare the filtered signal to a reference value and togenerate a shock sensor circuitry output signal in response, wherein theleakage tolerant input amplifier includes:an amplifier having anon-inverting input terminal, an inverting input terminal, and an outputterminal, the amplifier operable to receive and amplify the inputsignal, received across its input terminals, and an offset signal,generated by the leakage current of the input signal received at thenon-inverting output terminal, and to generate an amplified signal atthe output terminal in response; an output device operable to receivethe amplified signal from the output terminal and to regulate a controlcurrent in response; a first current mirror circuitry operable toreceive a bias current and to mirror the bias current to the outputdevice and to an output node; and a second current mirror circuitryoperable to receive the control current from the output device and tomirror the control current to the output node, and wherein the outputnode provides the amplified input signal at a value corresponding to thedifference between the bias current and the control current.
 16. Theshock sensor circuitry of claim 15, wherein the amplifier is anoperational amplifier and the inverting input terminal couples to theoutput device.
 17. A shock sensor circuitry for processing an inputsignal generated by a shock sensor in response to the shock sensordetecting a force, the shock sensor circuitry comprising:a leakagetolerant input amplifier having a direct current gain of around zero andoperable to receive the input signal including a leakage current and togenerate an amplified input signal in response; a filter circuitoperable to receive the amplified input signal and to filter theamplified input signal to generate a filtered signal; and a comparatoroperable to compare the filtered signal to a reference value and togenerate a shock sensor circuitry output signal in response, wherein thecomparator is a window comparator operable to compare the filteredsignal to an upper reference value and a lower reference value, thewindow comparator operable to generate the shock sensor circuitry outputsignal in an enabled state if the filtered signal is greater than theupper reference value or less than the lower reference value.
 18. Theshock sensor circuitry of claim 17, wherein the window comparatorincludes an upper comparator operable to compare the filtered signal tothe upper reference value and to generate an upper shock sensorcircuitry output signal in the enabled state if the filtered signal isgreater than the upper reference value, a lower comparator operable tocompare the filtered signal to the lower reference value and to generatea lower shock sensor circuitry output signal in the enabled state if thefiltered signal is less than the lower reference value, and an outputcircuit operable to enable the shock sensor circuitry output signal ifeither the upper shock sensor circuitry output signal or the lower shocksensor circuitry output signal is provided in the enabled state.
 19. Ashock sensor circuitry for processing an input signal generated by ashock sensor in response to the shock sensor detecting a force, theshock sensor circuitry comprising:a leakage tolerant input amplifierhaving a direct current gain of around zero and operable to receive theinput signal including a leakage current and to generate an amplifiedinput signal in response; a filter circuit operable to receive theamplified input signal and to filter the amplified input signal togenerate a filtered signal; and a comparator operable to compare thefiltered signal to a reference value and to generate a shock sensorcircuitry output signal in response, wherein the filter circuit includesa second order low pass filter and a high pass filter.
 20. The shocksensor circuitry of claim 19, whereinthe second order low pass filter isoperable to receive and process the amplified input signal and togenerate a low pass filtered signal in response; the high pass filteroperable is receive and process the low pass filtered signal and togenerate a high pass filtered signal in response; and the filter circuitfurther includesa summing amplifier operable to add the low passfiltered signal and the high pass filtered signal and to generate thefiltered signal in response.
 21. The shock sensor circuitry of claim 20,wherein the filter circuit further includes:a boost amplifier operableto receive and amplify the high pass filtered signal and to generate anamplified high pass filtered signal in response, and wherein theamplified high pass filtered signal is provided to the summing amplifieralong with the low pass filtered signal.
 22. The shock sensor circuitryof claim 20, wherein the summing amplifier is a variable gain amplifierwith a programmable gain.
 23. A shock sensor circuitry for processing aninput signal generated by a shock sensor in response to the shock sensordetecting a force, the shock sensor circuitry comprising:a leakagetolerant input amplifier having a direct current gain of around zero andoperable to receive the input signal including a leakage current and togenerate an amplified input signal in response; a filter circuitoperable to receive the amplified input signal and to filter theamplified input signal to generate a filtered signal; and a comparatoroperable to compare the filtered signal to a reference value and togenerate a shock sensor circuitry output signal in response, wherein theinput signal is generated by a first shock sensor in response to thefirst shock sensor detecting a force in a first direction, and a secondinput signal is generated by a second shock sensor in response to thesecond shock sensor detecting a force in a second direction, and furthercomprising:a second leakage tolerant input amplifier operable to receivethe second input signal including a second leakage current and togenerate a second amplified input signal in response, the secondamplified input signal having a direct current gain of around zero; asecond filter circuit operable to receive the second amplified inputsignal and to filter the second amplified input signal to generate asecond filtered signal; and a second comparator operable to compare thesecond filtered signal to a second reference value and to generate asecond shock sensor circuitry output signal in response.
 24. The shocksensor circuitry of claim 23, wherein a third input signal is generatedby a third shock sensor in response to the third shock sensor detectinga force in a third direction, and further comprising:a third leakagetolerant input amplifier operable to receive the third input signalincluding a third leakage current and to generate a third amplifiedinput signal in response, the third amplified input signal having adirect current gain of around zero; a third filter circuit operable toreceive the third amplified input signal and to filter the thirdamplified input signal to generate a third filtered signal; and a thirdcomparator operable to compare the third filtered signal to a thirdreference value and to generate a third shock sensor circuitry outputsignal in response.
 25. A shock sensor circuitry for processing an inputsignal generated by a shock sensor in response to the shock sensordetecting a force, the shock sensor circuitry comprising:a leakagetolerant input amplifier having a direct current gain of around zero andoperable to receive the input signal including a leakage current and togenerate an amplified input signal in response; a filter circuitoperable to receive the amplified input signal and to filter theamplified input signal to generate a filtered signal; and a comparatoroperable to compare the filtered signal to a reference value and togenerate a shock sensor circuitry output signal in response, wherein theinput signal is generated between a first terminal and a second terminalof the shock sensor, and the input signal is provided to the leakagetolerant input amplifier across an inverting input terminal and anon-inverting input terminal of the leakage tolerant input amplifier.26. The shock sensor circuitry of claim 25, wherein a bias resistor isprovided across the first terminal and the second terminal of the shocksensor, and a capacitor and a resistor are provided between the firstterminal of the shock sensor and the inverting terminal of the leakagetolerant input amplifier.
 27. A shock sensor circuitry for processing aninput signal generated by a shock sensor in response to the shock sensordetecting a force, the shock sensor circuitry comprising:a leakagetolerant input amplifier having a direct current gain of around zero andoperable to receive the input signal including a leakage current and togenerate an amplified input signal in response; a filter circuitoperable to receive the amplified input signal and to filter theamplified input signal to generate a filtered signal; and a comparatoroperable to compare the filtered signal to a reference value and togenerate a shock sensor circuitry output signal in response, wherein theleakage tolerant input amplifier receives the leakage current in theform of an offset voltage generated by providing the leakage currentthrough a bias resistor.
 28. A method for amplifying a first inputsignal and an offset signal, the offset signal generated from a directcurrent leakage current, to generate an amplified input signal with adirect current gain of about zero, the method comprising the stepsof:receiving the first input signal and the offset signal generated fromthe direct current leakage current; amplifying the input signal and theoffset signal with an operational amplifier circuitry to generate anamplified signal at an output terminal with the direct current gain andan alternating current gain; providing the amplified signal to an outputdevice coupled to the output terminal of the operational amplifiercircuitry; mirroring a bias current to the output device and to anoutput node; regulating a control current in response to receiving theamplified signal and the bias current; mirroring the control current tothe output node; and generating the amplified input signal at anamplified value corresponding to the difference between the bias currentand the control current as provided at the output node such that theamplified input signal is generated at or near zero when the offsetsignal is provided at a constant value.
 29. The method of claim 28,wherein the input signal is provided from a piezoelectric shock sensor.30. The method of claim 28, wherein the output device is a field-effecttransistor.